Answer / seetharamukg

Signals updates a value after some "delta" time or at the
end of the process. But variable updates a value immediately.

Both variable and signals are synthesizable.
Designer should know hoe to use these 2 objects.

Ex: Signal usage
Library IEEE;
use IEEE.std_logic_1164.all;
entity xor_sig is
port (
A, B, C: in STD_LOGIC;
X, Y: out STD_LOGIC
);
end xor_sig;
architecture SIG_ARCH of xor_sig is
signal D: STD_LOGIC;
begin
SIG:process (A,B,C)
begin
D <= A; -- ignored !!
X <= C xor D;
D <= B; -- overrides !!
Y <= C xor D;
end process;
end SIG_ARCH;

Variable usage:
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity xor_var is
port (
A, B, C: in STD_LOGIC;
X, Y: out STD_LOGIC
);
end xor_var;
architecture VAR_ARCH of xor_var is
begin
VAR:process (A,B,C)
variable D: STD_LOGIC;
begin
D := A;
X <= C xor D;
D := B;
Y <= C xor D;
end process;
end VAR_ARCH;

What are the different measures that are required to achieve the design for better yield?

0 Answers  

---

Explain how logical gates are controlled by Boolean logic?

0 Answers  

---

What happens if we increase the number of contacts or via from one metal layer to the next?

1 Answers   Infosys,

---

What are the different gates where boolean logic are applicable?

0 Answers  

---

What happens to delay if you increase load capacitance?

1 Answers   Google,

---

---

What are the different limitations in increasing the power supply to reduce delay?

2 Answers  

---

Explain the three regions of operation of a mosfet.

0 Answers  

---

Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

0 Answers   Infosys,

---

Differences between Array and Booth Multipliers?

0 Answers   Intel,

---

How does Vbe and Ic change with temperature?

0 Answers   Qualcomm,

---

Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?

1 Answers   IIT, Intel,

---

Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

---