Answer Posted / seetharamukg

Signals updates a value after some "delta" time or at the
end of the process. But variable updates a value immediately.

Both variable and signals are synthesizable.
Designer should know hoe to use these 2 objects.

Ex: Signal usage
Library IEEE;
use IEEE.std_logic_1164.all;
entity xor_sig is
port (
A, B, C: in STD_LOGIC;
X, Y: out STD_LOGIC
);
end xor_sig;
architecture SIG_ARCH of xor_sig is
signal D: STD_LOGIC;
begin
SIG:process (A,B,C)
begin
D <= A; -- ignored !!
X <= C xor D;
D <= B; -- overrides !!
Y <= C xor D;
end process;
end SIG_ARCH;

Variable usage:
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity xor_var is
port (
A, B, C: in STD_LOGIC;
X, Y: out STD_LOGIC
);
end xor_var;
architecture VAR_ARCH of xor_var is
begin
VAR:process (A,B,C)
variable D: STD_LOGIC;
begin
D := A;
X <= C xor D;
D := B;
Y <= C xor D;
end process;
end VAR_ARCH;

Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

1487

---

Describe the various effects of scaling?

4796

---

What types of CMOS memories have you designed? What were their size? Speed?

4665

---

Cross section of a PMOS transistor?

4776

---

For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

1260

---

Tell me how MOSFET works.

2431

---

Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

3381

---

Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

1302

---

Explain Cross section of a PMOS transistor?

1238

---

What does it mean “the channel is pinched off”?

1360

---

What products have you designed which have entered high volume production?

2450

---

Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3871

---

Explain why present VLSI circuits use MOSFETs instead of BJTs?

1157

---

For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

1282

---

Design an 8 is to 3 encoder using 4 is to encoder?

1338

---