Why is Extraction performed?

1 Answers   Intel,

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In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?

0 Answers  

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Explain the Working of a 2-stage OPAMP?

0 Answers   Intel,

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Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,

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What are the different limitations in increasing the power supply to reduce delay?

2 Answers  

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What is the most complicated/valuable program you written in C/C++?

23 Answers   HCL, IBM, Intel, TCS, TVS, Wipro,

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What are the steps involved in preventing the metastability?

0 Answers  

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Differences between netlist of HSPICE and Spectre?

1 Answers   Intel,

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Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,

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Explain the working of 4-bit Up/down Counter?

0 Answers   Intel,

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Explain what is the depletion region?

0 Answers  

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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