What are the steps required to solve setup and hold violations in vlsi?

0 Answers  

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For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

0 Answers   Infosys,

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What are the different measures that are required to achieve the design for better yield?

0 Answers  

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What types of CMOS memories have you designed? What were their size? Speed?

0 Answers   e-tec, Intel,

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What are the different design techniques required to create a layout for digital circuits?

0 Answers  

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Id vs. Vds Characteristics of NMOS and PMOS transistors?

1 Answers   Brillient, Intel, ISRO,

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Advantages and disadvantages of Mealy and Moore?

2 Answers   Intel,

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What is the critical path in a SRAM?

0 Answers  

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What are the main issues associated with multiprocessor caches and how might you solve them?

0 Answers   Intel,

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Explain what is slack?

0 Answers  

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For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

0 Answers   Intel,

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what is the difference between the testing and verification?

1 Answers   Intel,

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