How do you size NMOS and PMOS transistors to increase the threshold voltage?

0 Answers   Infosys,

---

What are the different limitations in increasing the power supply to reduce delay?

2 Answers  

---

How can you construct both PMOS and NMOS on a single substrate?

0 Answers   IBM, Intel,

---

Give the cross-sectional diagram of the cmos.

0 Answers  

---

For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

0 Answers   Infosys,

---

---

What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

0 Answers   Intel,

---

In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

0 Answers   Infosys,

---

While using logic design, explain the various steps that r followed to obtain the desirable design in a well defined manner?

1 Answers   Intel,

---

Given a circuit and asked to tell the output voltages of that circuit?

1 Answers   Intel, Omega Healthcare,

---

Explain the difference between write through and write back cache.

2 Answers   Intel,

---

What is Noise Margin? Explain the procedure to determine Noise Margin?

4 Answers   Amkor, Cisco, Infosys, Intel,

---

For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

3 Answers   Intel,

---