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Infosys VLSI Interview Questions
Questions Answers Views Company eMail

What are the limitations in increasing the power supply to reduce delay?

 2 12236

How does Resistance of the metal lines vary with increasing thickness and increasing length?

 3 12399

What happens if we increase the number of contacts or via from one metal layer to the next?

 1 6722

In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

 3606

Insights of a 2 input NOR gate. Explain the working?

 1 2882

Differences between DRAM and SRAM?

 14 68280

What types of high speed CMOS circuits have you designed?

 2 13524

Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

 644

Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

 906

In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

 690

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.

 705

Draw the stick diagram of a NOR gate. Optimize it

 766

Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

 729

Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

 679

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

 687

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Infosys VLSI Interview Questions


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