Tell me how BJT works.

2 Answers  

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How to find the read failiure probablity in SRAM?

2 Answers  

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Insights of a 4bit adder/Sub Circuit?

0 Answers   Intel,

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What is the difference between fifo and the memory?

6 Answers   DewSoft, Intel, Pentagon Rugged Systems,

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Explain how Verilog is different to normal programming language?

0 Answers  

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What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

0 Answers   Infosys,

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Give the expression for CMOS switching power dissipation?

2 Answers   Cypress Semiconductor,

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What is validation?

2 Answers   Intel,

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What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?

4 Answers   Intel,

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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Write a program to explain the comparator?

0 Answers  

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What are the ways to Optimize the Performance of a Difference Amplifier?

0 Answers  

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