Suppose you have a combinational circuit between two
registers driven by a clock. What will you do if the delay
of the combinational circuit is greater than your clock signal?
Answers were Sorted based on User's Feedback
Answer / ravi desai
Put even number of not gates between clocks of reg A and
Reg B. The not gates will introduce delay between clock of
reg A and reg B.
Is This Answer Correct ? | 5 Yes | 2 No |
Answer / priyesh
If the circuit given is asynchronous then we can lower the
delay by supplying the same clock to all flip flops i.e.
making the circuit synchronous.
Another way is by adding NOT gates between clock and register
Is This Answer Correct ? | 0 Yes | 0 No |
Answer / ravi desai
put even number not gates between clock of reg A and Reg B.
the not gates will introduce delay.
Is This Answer Correct ? | 2 Yes | 4 No |
What are the different types of arithmetic operations that can be performed by the 8085 microprocessor?
Device density on a microprocessor/chip?
What are hardware interrupts?
What is the difference between isr & function call?
How is the system clock calculated in the 8085?
How can interrupts be classified in the 8086?
What happens during DMA transfer?
How is EPROM generally erased
What jobs alu of 8085 can perform?
How can the signals of the 8086 be categorised?
Define the type of interrupts in the 8085 processor?
In which T-state does the CPU sends the address o memory or I/O and the ALE signal for Demultiplexing